[PATCH] D115133: [RISCV] Support immediate vtype of VSETVLI/VSETIVLI in asm parser
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 7 09:24:12 PST 2021
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1577
+ // vsetivli rd, uimm, 0xabc or vsetvli rd, rs1, 0xabc
+ if (getLexer().is(AsmToken::Integer)) {
+ int64_t Val = getLexer().getTok().getIntVal();
----------------
benshi001 wrote:
> craig.topper wrote:
> > Does binutils only except literal integers or does it support expressions?
> I have tested the newest master of binutils,
>
> 1. it does not support vtype being an expression, in fact there is no expression cases in binutils's unit tests.
>
> 2. it still generate wrong dissambly against illegal vtype, for example, larger types such as `e128`
Our internal version of bintuils does accept this `vsetvli x0, x0, 0xff + 1`. I haven't checked binutils compiled with public sources, but I expect they would be the same.
The disassembly bugs have been fixed in our internal branch of binutils. I'll find out when they'll be fixed in publicly available sources.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D115133/new/
https://reviews.llvm.org/D115133
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