[PATCH] D114800: [PowerPC] Replace MFVSRLD with MFVSRD when the vector is symmetrical

ChenZheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 30 17:50:45 PST 2021

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shchenz added a comment.

Can we fix this at the place where `MFVSRLD` is generated? (in DAG-ISEL?)


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D114800/new/

https://reviews.llvm.org/D114800

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