[PATCH] D114800: [PowerPC] Replace MFVSRLD with MFVSRD when the vector is symmetrical

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp created this revision.
stefanp added reviewers: lei, nemanjai.
Herald added subscribers: shchenz, kbarton, hiraditya.
stefanp requested review of this revision.
Herald added a project: LLVM.

The MFVSRD is faster than the MFVSRLD instruction and if the input vector is
symmetrical then both instructions produce the same result and we should prefer
the faster one.

This patch mainly looks at symmetrical situations that are known to arise after
a vector doubleword swap.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114800

Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/reduce_scalarization.ll
  llvm/test/CodeGen/PowerPC/vector-reduce-add.ll
  llvm/test/CodeGen/PowerPC/vector-reduce-and.ll
  llvm/test/CodeGen/PowerPC/vector-reduce-or.ll
  llvm/test/CodeGen/PowerPC/vector-reduce-smax.ll
  llvm/test/CodeGen/PowerPC/vector-reduce-smin.ll
  llvm/test/CodeGen/PowerPC/vector-reduce-umax.ll
  llvm/test/CodeGen/PowerPC/vector-reduce-umin.ll
  llvm/test/CodeGen/PowerPC/vector-reduce-xor.ll

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