[PATCH] D114640: [PowerPC] Handle Vector Sum Reducation

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp updated this revision to Diff 390103.
stefanp added a comment.

Split out the peephole optimization that would replace MFVSRLD with MFVSRD
when possible.

That part of the patch will be a new patch soon.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114640/new/

https://reviews.llvm.org/D114640

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
  llvm/test/CodeGen/PowerPC/vector-reduce-add.ll

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