[PATCH] D114640: [PowerPC] Handle Vector Sum Reducation

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1067
       }
+      case PPC::MFVSRLD:
+        // It is more efficient to use MFVSRD instead of MFVSRLD in cases where
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This is a more general and orthogonal peephole. Can you please separate this out to another patch and make it more general? This patch can then depend on that one.


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Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1072
+        MachineInstr *DefVecReg = getVRegDefOrNull(&VecInput, MRI);
+        if (DefVecReg->getOpcode() == PPC::VADDUDM) {
+          MachineOperand &AddInput1 = DefVecReg->getOperand(1);
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Please make this more general by implementing a separate function called something like `isVectorSymmetrical()` that will just check whether the two halves of the vector are the same. Then this can be flipped to an early exit condition.

P.S. Keep in mind that it is possible that `DefVecReg == nullptr` which would cause a crash when you call `DefVecReg->getOpcode()`.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D114640/new/

https://reviews.llvm.org/D114640