[PATCH] D113281: [AArch64][SVE] Generate ASRD instructions for power of 2 signed divides

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

The previous patch looked cleaner but had the issue of not working well for illegal types, whereas this patch works well but is a little more verbose than I was expected.  What about having the ASRD_MERGE_OP1 target specific node but introducing it as part of LowerFixedLengthVectorIntDivideToSVE.  I feel this will simplify the patch whilst maintaining it current capabilities and remove the frailty Eli described.  When it comes to optimising the intrinsic we could achieve this via instcombine.


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https://reviews.llvm.org/D113281