[PATCH] D113281: [AArch64][SVE] Generate ASRD instructions for power of 2 signed divides

Wed Nov 24 11:14:30 PST 2021

efriedma accepted this revision.
efriedma added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13596
+  SDValue SDiv =
+      IsIntrinsic
+          ? DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, N->getOperand(0),
----------------
bsmith wrote:
> efriedma wrote:
> > Do we really need to preserve the fact that the operation was originally an intrinsic?
> I believe so yes, the semantics of the predicate are different between SDIV_PRED and the intrinsics, hence why we have different patterns to select these.
Oh, I see, the intrinsic has an extra operand.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113281/new/

https://reviews.llvm.org/D113281