[PATCH] D113281: [AArch64][SVE] Generate ASRD instructions for power of 2 signed divides

[Bradley Smith via Phabricator via llvm-commits]

bsmith updated this revision to Diff 389807.
bsmith added a comment.

- Change approach again to be between the last two
  - Go back to matching asrd nodes in instruction selection
  - Create the asrd nodes during lowering rather than BuildSDIVPow2
  - This makes the patch cleaner whilst still supporting larger than legal types
  - Intrinsics will be handled in a separate patch in instcombine.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113281/new/

https://reviews.llvm.org/D113281

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
  llvm/test/CodeGen/AArch64/sve-sdiv-pow2.ll

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