[PATCH] D113353: [RISCV] Add scheduling resources for Vector pseudo instructions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2151
 
-multiclass VPseudoBinaryW_WV_WF {
-  defm "" : VPseudoBinaryW_WV;
-  defm "" : VPseudoBinaryW_WF;
+multiclass VPseudoVWALU_VV_VF {
+  defm "" : VPseudoBinaryW_VV,
----------------
Based on Fraser's FMUL and FDIV comments, this should be VFWALU


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2158
 
-multiclass VPseudoBinaryV_VM_XM_IM {
-  defm "" : VPseudoBinaryV_VM;
-  defm "" : VPseudoBinaryV_XM;
-  defm "" : VPseudoBinaryV_IM;
+multiclass VPseudoVWALU_WV_WF {
+  defm "" : VPseudoBinaryW_WV,
----------------
Same here


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2421
+
+multiclass VPseudoVWFRED_VS {
+  foreach m = MxList.m in {
----------------
VWFRED -> VFWRED to match the scheduler class name and instruction names


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113353/new/

https://reviews.llvm.org/D113353