[PATCH] D113353: [RISCV] Add scheduling resources for Vector pseudo instructions.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

Generally looks good to me, thanks @HsiangKai



================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2038
+
+multiclass VPseudoVMAX_VV_VX {
+  defm "" : VPseudoBinaryV_VV,
----------------
nit: `MINMAX`?


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2059
+
+multiclass VPseudoVMUL_VV_VF {
+  defm "" : VPseudoBinaryV_VV,
----------------
nit: `VFMUL`? I know `VF` helps disambiguate it but I think people are generally more opcode focused. 


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2066
+
+multiclass VPseudoVDIV_VV_VF {
+  defm "" : VPseudoBinaryV_VV,
----------------
nit: `VFDIV`?


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2073
+
+multiclass VPseudoVRDIV_VF {
+  defm "" : VPseudoBinaryV_VF,
----------------
`VFRDIV`


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2215
+
+
+multiclass VPseudoVCALUM_V_X<string Constraint> {
----------------
nit: can probably get rid of this extra space


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D113353/new/

https://reviews.llvm.org/D113353