[PATCH] D113281: [AArch64][SVE] Generate ASRD instructions for power of 2 signed divides

Wed Nov 24 04:02:18 PST 2021

bsmith added a comment.

In D113281#3149637 <https://reviews.llvm.org/D113281#3149637>, @efriedma wrote:

> If I'm following correctly, this patch is doing three things:
>
> 1. It adds patterns to select asrd if the RHS is a power of two.
> 2. It turns sdiv of negative power of two into sdiv+neg.
> 3. It makes sdiv of i8 and i16 legal if the RHS is a power of two.
>
> The first two are clearly fine. (3) is a bit fragile; usually legality doesn't depend on the structure of the operands, only their type.  The legalizer won't rerun if the structure of the operand changes. If you're specifically checking for a splat of a constant, I guess it's okay.

I agree on this, however there didn't seem to be a good alternative that would allow catching both the intrinsics as well as larger than legal fixed types (i.e. using `BuildSDIVPow2` directly).

================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13596
+  SDValue SDiv =
+      IsIntrinsic
+          ? DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, N->getOperand(0),
----------------
efriedma wrote:
> Do we really need to preserve the fact that the operation was originally an intrinsic?
I believe so yes, the semantics of the predicate are different between SDIV_PRED and the intrinsics, hence why we have different patterns to select these.

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