[PATCH] D113967: [RISCV] Reverse the order of loading/storing callee-saved registers.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

In D113967#3139233 <https://reviews.llvm.org/D113967#3139233>, @jrtc27 wrote:

> In-order superscalar is a good point though, and the FU740 is precisely such a pipeline where you can issue both a load and a branch in the same cycle, so I guess the current codegen is hurting a noticeable amount there.

Yeah, in-order superscalar is the case. We found the performance downgrade in U74 compared with GCC codegen.


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