[PATCH] D113967: [RISCV] Reverse the order of loading/storing callee-saved registers.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

Just some comment nits, otherwise ready to land IMO



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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:1070
+  // Keep the same order as in the prologue. There is no need to reverse the
+  // order in the epilogue. In addition, return address will be restored first
+  // in the epilogue. It increases the opportunity to fill the bubbles between
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Missing "the" before "return address"


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:1071
+  // order in the epilogue. In addition, return address will be restored first
+  // in the epilogue. It increases the opportunity to fill the bubbles between
+  // loading $RA and return by $RA.
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I wouldn't talk about filling bubbles, there may not be any anyway. Just say it avoids potential load-to-use data hazards, as in the commit message.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:1072
+  // in the epilogue. It increases the opportunity to fill the bubbles between
+  // loading $RA and return by $RA.
   // loadRegFromStackSlot can insert multiple instructions.
----------------
RISC-V registers don't have a $ prefix.


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  https://reviews.llvm.org/D113967/new/

https://reviews.llvm.org/D113967