[PATCH] D113967: [RISCV] Reverse the order of loading/storing callee-saved registers.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

There is still lot of low-end RISC-V CPU used in embedded world, which might use such u-arch and benefit for such code gen change as I know :p


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113967/new/

https://reviews.llvm.org/D113967