[PATCH] D113967: [RISCV] Reverse the order of loading/storing callee-saved registers.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

In-order superscalar is a good point though, and the FU740 is precisely such a pipeline where you can issue both a load and a branch in the same cycle, so I guess the current codegen is hurting a noticeable amount there.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D113967/new/

https://reviews.llvm.org/D113967