[PATCH] D113967: [RISCV] Reverse the order of loading/storing callee-saved registers.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

Sure, I realise that if you have an extremely basic pipeline without forwarding then it does matter. I just didn't think anyone seriously cared about such microarchitectures in this day and age, or if they did then they at least didn't expect any kind of half-decent performance out of them. Not against this change, just surprised it's ever particularly noticeable.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113967/new/

https://reviews.llvm.org/D113967