[PATCH] D113967: [RISCV] Reverse the order of loading/storing callee-saved registers.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

An ASCII pipeline diagram to demonstrate why reorder that could help:

Consider a typical RISC 5 stage pipeline CPU:

IF:  Instruction Fetch
ID:  Instruction Decode
EXE: Instruction Execute
MEM: Memory Access
WB:  Write Back

Assume we need 2 cycle to read memory and NO forwording.

  lw s1, 4(sp) # 4-byte Folded Reload
  lw s0, 8(sp) # 4-byte Folded Reload
  lw ra, 12(sp) # 4-byte Folded Reload
  addi sp, sp, 16
  ret



| Cycle  | IF    | ID    | EXE   | MEM   | WB    | Comment                                  |
| N      | lw s1 |       |       |       |       |
| N + 1  | lw s0 | lw s1 |       |       |       |
| N + 2  | lw ra | lw s0 | lw s1 |       |       |
| N + 3  | addi  | lw ra | lw s0 | lw s1 |       | Reading sp + 4 (1st cycle)               |
| N + 4  | addi  | lw ra | lw s0 | lw s1 |       | Reading sp + 4 (stall for 2nd cycle)     |
| N + 5  | ret   | addi  | lw ra | lw s0 | lw s1 | Reading sp + 8 (1st cycle)               |
| N + 6  | ret   | addi  | lw ra | lw s0 |       | Reading sp + 8 (stall for 2st cycle)     |
| N + 7  |       | ret   | addi  | lw ra | lw s0 | Reading sp + 12 (1st cycle)              |
| N + 8  |       | ret   | addi  | lw ra |       | Reading sp + 12 (stall for 2st cycle)    |
| N + 9  |       | ret   |       | addi  | lw ra | ret stall due to ra isn't ready to read. |
| N + 10 |       |       | ret   |       | addi  |                                          |
|

...

  lw ra, 12(sp) # 4-byte Folded Reload
  lw s0, 8(sp) # 4-byte Folded Reload
  lw s1, 4(sp) # 4-byte Folded Reload
  addi sp, sp, 16
  ret



| Cycle | IF    | ID    | EXE   | MEM   | WB    | Comment                               |
| N     | lw ra |       |       |       |       |
| N + 1 | lw s0 | lw ra |       |       |       |
| N + 2 | lw s1 | lw s0 | lw ra |       |       |
| N + 3 | addi  | lw s1 | lw s0 | lw ra |       | Reading sp + 12 (1st cycle)           |
| N + 4 | addi  | lw s1 | lw s0 | lw ra |       | Reading sp + 12 (stall for 2nd cycle) |
| N + 5 | ret   | addi  | lw s1 | lw s0 | lw ra | Reading sp + 8 (1st cycle)            |
| N + 6 | ret   | addi  | lw s1 | lw s0 |       | Reading sp + 8 (stall for 2st cycle)  |
| N + 7 |       | ret   | addi  | lw s1 | lw s0 | Reading sp + 12 (1st cycle)           |
| N + 8 |       | ret   | addi  | lw s1 |       | Reading sp + 12 (stall for 1st cycle) |
| N + 9 |       |       | ret   | addi  | lw s1 | NO stall for ret!                     |
|

...


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https://reviews.llvm.org/D113967