[PATCH] D113967: [RISCV] Reverse the order of loading/storing callee-saved registers.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Additional context I got from Andrew Waterman

  The ability to partially hide the latency of a cache miss using a non-blocking cache is more of a secondary concern.  The latency of a load hit is the parameter we're more sensitive to.
  
  The problem manifests primarily in in-order processors, where the ret instruction will be stalled until its operands are available, hence speculative execution past the ret instruction will not occur.  Single-issue in-order processors with at least two cycles of load-use delay are likely to manifest this stall.  In-order superscalars are likely to manifest this stall even with smaller load-use delays.
  
  While this is much less of an issue for out-of-order processors, this change has some value even there: the earlier an instructions' operands are available, the lower its occupancy in the issue window, reducing pressure on issue-window capacity.




Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D113967/new/

https://reviews.llvm.org/D113967