[PATCH] D113802: [PowerPC] Fix 32bit vector insert instructions for ISA3.1
Nemanja Ivanovic via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 15 06:00:02 PST 2021
nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.
LGTM other than minor nits.
================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:2835
+// Immediate vector insert element
+let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in {
+ foreach Idx = [0, 1, 2, 3] in {
----------------
Why did you pull this out of the block above? The `Predicates` seem to be exactly the same.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D113802/new/
https://reviews.llvm.org/D113802
More information about the llvm-commits
mailing list