[PATCH] D113802: [PowerPC] Fix 32bit vector insert instructions for ISA3.1

[Lei Huang via Phabricator via llvm-commits]

lei added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:2835
+// Immediate vector insert element
+let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in {
+  foreach Idx = [0, 1, 2, 3] in {
----------------
nemanjai wrote:
> Why did you pull this out of the block above? The `Predicates` seem to be exactly the same.
It's because of the complexity. For vector insert double, the original pattern generated:
```
lfd f0, 0(r5)
xxmrghd v2, v2, vs0
```
seem to be better then forcing it to use VINSDRX
```
ld r3, 0(r5)
li r4, 0
vinsdrx v2, r4, r3
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D113802/new/

https://reviews.llvm.org/D113802