[PATCH] D113802: [PowerPC] Fix 32bit vector insert instructions for ISA3.1
Nemanja Ivanovic via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 15 05:31:32 PST 2021
nemanjai added a comment.
Please rebase. Does not apply cleanly to ToT.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10768
// On P10, we have legal lowering for constant and variable indices for
- // integer vectors.
+ // integer vectors and float vectors.
if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
----------------
s/integer vectors and float vectors/all vectors
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D113802/new/
https://reviews.llvm.org/D113802
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