[PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.

Fraser Cormack via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 26 06:32:28 PDT 2021

Previous message: [PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.
Next message: [PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

frasercrmck added a comment.

I'm not sure I am the best person to accept as I'm not super familiar with anything related to Zvlsseg. Sorry!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110250/new/

https://reviews.llvm.org/D110250

Previous message: [PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.
Next message: [PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list