[PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.

Hsiangkai Wang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Oct 25 17:12:35 PDT 2021

Previous message: [PATCH] D112500: [lld-macho] Put GOT into `__DATA` segment where appropriate
Next message: [PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

HsiangKai added a comment.

Ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110250/new/

https://reviews.llvm.org/D110250

Previous message: [PATCH] D112500: [lld-macho] Put GOT into `__DATA` segment where appropriate
Next message: [PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list