[PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM other than the comment about adding a comment.



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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:391
+                  !eq(lmul, 1):
+                  [8, 9, 10, 11, 12, 13, 14, 15,
+                   16, 17, 18, 19, 20, 21, 22, 23,
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Probably worth a comment explaining what this is doing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110250/new/

https://reviews.llvm.org/D110250