[PATCH] D111856: [AArch64][GlobalISel] combine (and (or x, c1), c2) => (and x, c2) iff c1 & c2 == 0

[Jessica Paquette via Phabricator via llvm-commits]

paquette added inline comments.


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Comment at: llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp:4030
+  Register Mask = MI.getOperand(2).getReg();
+  MatchInfo = [=](MachineIRBuilder &B) { B.buildAnd(Dst, Src, Mask); };
+  return true;
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Could you just replace the operands of the existing G_AND rather than building a new G_AND?


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Comment at: llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir:5
+# REQUIRES: asserts
+
+...
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maybe a vector testcase too?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D111856/new/

https://reviews.llvm.org/D111856