[PATCH] D111856: [AArch64][GlobalISel] combine (and (or x, c1), c2) => (and x, c2) iff c1 & c2 == 0

[Jon Roelofs via Phabricator via llvm-commits]

jroelofs updated this revision to Diff 380086.
jroelofs added a comment.

Modify the G_AND in-place, and ignore vector types.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111856/new/

https://reviews.llvm.org/D111856

Files:
  llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
  llvm/include/llvm/Target/GlobalISel/Combine.td
  llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/combine-and-or-disjoint-mask.mir

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