[PATCH] D111304: [RISCV] Reorder the vector register allocation order.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

In D111304#3057612 <https://reviews.llvm.org/D111304#3057612>, @rogfer01 wrote:

> No objection with this, I guess it is for consistency with GPRs, right?

Yes. Starting with v25 is also strange. It should be an 8x number for LMUL may be 8. To be consistent with GPR to start with argument registers may be a way to go.


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https://reviews.llvm.org/D111304