[PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

Yeah I can see that a consistent order being the same is probably a good thing, even if we don't see COPYs being removed.



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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:400
+                  !eq(lmul, 4):
+                  [7,
+                   2, 3, 4, 5, 6,
----------------
Are these line breaks intentional?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110250/new/

https://reviews.llvm.org/D110250