[PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:400
+                  !eq(lmul, 4):
+                  [7,
+                   2, 3, 4, 5, 6,
----------------
frasercrmck wrote:
> Are these line breaks intentional?
Yes, I try to group them as (25 ~ 31), (8 ~ 24), (1 ~ 7) after multiply.


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  https://reviews.llvm.org/D110250/new/

https://reviews.llvm.org/D110250