[PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I'm not sure I've seen a test where this removed any copies yet. I asked Kai about the allocation order while investigating an extra copy, but this change did not remove the copy on that test. But I still think it makes sense to allocate registers in a consistent order.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110250/new/

https://reviews.llvm.org/D110250