[PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.
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In D110250#3017188 <https://reviews.llvm.org/D110250#3017188>, @rogfer01 wrote:

> I think this is reasonable. I wonder if you have a small test that shows we can avoid copies this way. Unless I missed one case, the updates to the tests only show different registers being used (I understand they're small enough and copies are not a problem for them).
>
> Perhaps you can precommit a test that will have better code generation with this change?

Sorry for replying late. I have no way to create a small test case to demonstrate it. Register allocator is smart enough to avoid redundant copy.
The redundant copy is found in our internal application.


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