[PATCH] D111048: [ARM] Introduce a MQPRCopy

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: samtebbs, SjoerdMeijer, ostannard, simon_tatham.
Herald added subscribers: hiraditya, kristof.beyls, qcolombet.
dmgreen requested review of this revision.
Herald added a project: LLVM.

Currently when creating tail predicated loops, we need to validate that all the live-outs of a loop will be equivalent with and without tail predication, and if they are not we cannot legally create a tail-predicated loop, leaving expensive vctp and vpst instructions in the loop. These notably can include register-allocation instructions like stack loads and stores, and copys lowered from COPYs to MVE_VORRs.

Instead of trying to prove this is valid late in the pipeline, this patch introduces a MQPRCopy pseudo instruction that COPY is lowered to. This can then either be converted to a MVE_VORR where possible, or to a couple of VMOVD instructions if not. This way they do not behave differently within and outside of tail-predications regions, and we can know by construction that they are always valid. The idea is that we can do the same with stack load and stores, converting them to VLDR/VSTR or VLDM/VSTM where required to prove tail predication is always valid.

This does unfortunately mean inserting multiple VMOVD instructions, instead of a single MVE_VORR, but my experiments show it to be an improvement in general.


https://reviews.llvm.org/D111048

Files:
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir

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