[PATCH] D110829: [X86] Copy registers in reverse order in convertToThreeAddress

[Jay Foad via Phabricator via llvm-commits]

foad updated this revision to Diff 377249.
foad added a comment.

Switch to MIR test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110829/new/

https://reviews.llvm.org/D110829

Files:
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/test/CodeGen/X86/twoaddr-mul2.mir


Index: llvm/test/CodeGen/X86/twoaddr-mul2.mir
===================================================================
--- llvm/test/CodeGen/X86/twoaddr-mul2.mir
+++ llvm/test/CodeGen/X86/twoaddr-mul2.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=x86_64-unknown -mcpu=haswell -run-pass=twoaddressinstruction %s -o - | FileCheck %s
 
-# FIXME: The killed flag should be on the second COPY from [[COPY]], not the first one.
+# Check that we don't have any uses of [[COPY]] after it is killed.
 ---
 name: test_mul_by_2
 tracksRegLiveness: true
@@ -13,9 +13,8 @@
     ; CHECK: liveins: $edi
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY killed $edi
-    ; CHECK-NEXT: undef %2.sub_32bit:gr64 = COPY killed [[COPY]]
-    ; CHECK-NEXT: undef %3.sub_32bit:gr64_nosp = COPY [[COPY]]
-    ; CHECK-NEXT: [[LEA64_32r:%[0-9]+]]:gr32 = LEA64_32r killed %2, 1, killed %3, 0, $noreg
+    ; CHECK-NEXT: undef %2.sub_32bit:gr64_nosp = COPY [[COPY]]
+    ; CHECK-NEXT: [[LEA64_32r:%[0-9]+]]:gr32 = LEA64_32r killed %2, 1, killed %2, 0, $noreg
     ; CHECK-NEXT: $eax = COPY killed [[LEA64_32r]]
     ; CHECK-NEXT: RET 0, killed $eax
     %0:gr32 = COPY killed $edi
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.cpp
+++ llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -1532,13 +1532,6 @@
     else
       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
 
-    bool isKill;
-    Register SrcReg;
-    MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
-    if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
-                        SrcReg, isKill, ImplicitOp, LV))
-      return nullptr;
-
     const MachineOperand &Src2 = MI.getOperand(2);
     bool isKill2;
     Register SrcReg2;
@@ -1547,6 +1540,20 @@
                         SrcReg2, isKill2, ImplicitOp2, LV))
       return nullptr;
 
+    bool isKill;
+    Register SrcReg;
+    MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
+    if (Src.getReg() == Src2.getReg()) {
+      // Don't call classify LEAReg a second time on the same register, in case
+      // the first call inserted a COPY from Src2 and marked it as killed.
+      isKill = isKill2;
+      SrcReg = SrcReg2;
+    } else {
+      if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true,
+                          SrcReg, isKill, ImplicitOp, LV))
+        return nullptr;
+    }
+
     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
     if (ImplicitOp.getReg() != 0)
       MIB.add(ImplicitOp);


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