[PATCH] D110053: [AMDGPU] Add a regclass flag for scalar registers

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp:1173
     if (Desc.OpInfo[I].RegClass == -1 ||
-        !TRI->isVGPRClass(TRI->getRegClass(Desc.OpInfo[I].RegClass)))
+        !TRI->isVSSuperClass(TRI->getRegClass(Desc.OpInfo[I].RegClass)))
       continue;
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rampitec wrote:
> Why do you need to change this?
I assumed that check is specifically for VS_32/VS_64 classes. Isn't it the case?


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:138
+  // TODO: This flag is currently set for all regclasses other than vectors.
+  // Some of them aren't truly GPRs, TTMP for instance. It won't be a problem
+  // as long as they remain unallocatable.
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rampitec wrote:
> TTMP is scalar.
I will use another reference.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:794
   let HasVGPR = 1;
+  let HasSGPR = 1;
 }
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rampitec wrote:
> It does not have SGPRs.
I tried to associate them with the closest regtype (either VGPR or SGPR). 
I can remove it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110053/new/

https://reviews.llvm.org/D110053