[PATCH] D110053: [AMDGPU] Add a regclass flag for scalar registers

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp:1173
     if (Desc.OpInfo[I].RegClass == -1 ||
-        !TRI->isVGPRClass(TRI->getRegClass(Desc.OpInfo[I].RegClass)))
+        !TRI->isVSSuperClass(TRI->getRegClass(Desc.OpInfo[I].RegClass)))
       continue;
----------------
Why do you need to change this?


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:138
+  // TODO: This flag is currently set for all regclasses other than vectors.
+  // Some of them aren't truly GPRs, TTMP for instance. It won't be a problem
+  // as long as they remain unallocatable.
----------------
TTMP is scalar.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:794
   let HasVGPR = 1;
+  let HasSGPR = 1;
 }
----------------
It does not have SGPRs.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110053/new/

https://reviews.llvm.org/D110053