[PATCH] D110053: [AMDGPU] Add a regclass flag for scalar registers

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp:1173
     if (Desc.OpInfo[I].RegClass == -1 ||
-        !TRI->isVGPRClass(TRI->getRegClass(Desc.OpInfo[I].RegClass)))
+        !TRI->isVSSuperClass(TRI->getRegClass(Desc.OpInfo[I].RegClass)))
       continue;
----------------
cdevadas wrote:
> rampitec wrote:
> > Why do you need to change this?
> I assumed that check is specifically for VS_32/VS_64 classes. Isn't it the case?
SDWA cannot use SGPR operand, the original instruction can. So if the operand is not a VGPR it should bail. isVGPRClass() is correct here.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:794
   let HasVGPR = 1;
+  let HasSGPR = 1;
 }
----------------
cdevadas wrote:
> rampitec wrote:
> > It does not have SGPRs.
> I tried to associate them with the closest regtype (either VGPR or SGPR). 
> I can remove it.
It has VGPRs and nothing more.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110053/new/

https://reviews.llvm.org/D110053