[PATCH] D110053: [AMDGPU] Add a regclass flag for scalar registers
Christudasan Devadasan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 20 01:27:30 PDT 2021
cdevadas created this revision.
cdevadas added reviewers: rampitec, arsenm.
Herald added subscribers: foad, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
cdevadas requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.
Along with vector RC flags, this scalar flag will
make various regclass queries like `isVGPR` more
accurate.
Regclasses other than vectors are currently set
with the new flag even though certain unallocatable
classes like TTMP_* aren't truly scalars. It would
be ok as long as they remain unallocatable.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D110053
Files:
llvm/lib/Target/AMDGPU/SIDefines.h
llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
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