[PATCH] D109963: [AArch64] Split bitmask immediate of bitwise AND operation

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Does this need to be a custom emitter? That doesn't seem like a standard way of handling this. Could it be a AArch64DAGToDAGISel select from AND?

>From what I can see it appears to be a different transform on `AND X, C`, emitting two `AND`'s as opposed to an `AND` and some `MOVI`'s. It might be possible to do it through tblgen with a correct XForms on ImmLeafs, but keeping the logic together in AArch64DAGToDAGISel might be simpler.


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  https://reviews.llvm.org/D109963/new/

https://reviews.llvm.org/D109963