[PATCH] D109963: [AArch64] Split bitmask immediate of bitwise AND operation

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 added a comment.

In D109963#3006164 <https://reviews.llvm.org/D109963#3006164>, @dmgreen wrote:

> Does this need to be a custom emitter? That doesn't seem like a standard way of handling this. Could it be a AArch64DAGToDAGISel select from AND?
>
> From what I can see it appears to be a different transform on `AND X, C`, emitting two `AND`'s as opposed to an `AND` and some `MOVI`'s. It might be possible to do it through tblgen with a correct XForms on ImmLeafs, but keeping the logic together in AArch64DAGToDAGISel might be simpler.

Thanks for good suggestion. @dmgreen

I have tried to implement it on ISelDAG level. There are already patterns to fold `and` node. After this transformation on ISelDAGToDAG, I was able to see the patterns failed to match. If we can guarantee the pattern for this transformation is matched after matching other patterns related to `and`, it could be ok to implement it on ISelDAG level.  Maybe, we could add `AddedComplexity` to the pattern for this transformation but I thought the CustomInserter is better than it because it guarantees all pattern matching is done.


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