[PATCH] D109900: [AMDGPU] Filtering out the inactive lanes bits when lowering copy to SCC

[Ruiling, Song via Phabricator via llvm-commits]

ruiling added a reviewer: arsenm.
ruiling added a comment.

> When we pass the scalar i1 values to uniform VALU instructions 
> we use the fllowing representation: false - 0, true - 0xffffffffffffffff. 
> VALU instructions only process the olanes that are active, that is controlled by the EXEC mask.
> We need to filter out odd bits when copy the computation result back to SCC.

Could you add some more description what's going on in failure cases? So that is easy for others to understand the problem. And we also need a test to show the problem.


Repository:
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  https://reviews.llvm.org/D109900/new/

https://reviews.llvm.org/D109900