[PATCH] D109900: [AMDGPU] Filtering out the inactive lanes bits when lowering copy to SCC

[Alexander via Phabricator via llvm-commits]

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SALU i1 representation is just a one bit but VALU is 64bits.

  When we pass the scalar i1 values to uniform VALU instructions 
  we use the fllowing representation: false - 0, true - 0xffffffffffffffff. 
  VALU instructions only process the olanes that are active, that is controlled by the EXEC mask.
  We need to filter out odd bits when copy the computation result back to SCC.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109900

Files:
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

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