[PATCH] D109295: [X86] Handle inverted inputs when matching VPTERNLOG from 2 binary ops.

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added a comment.

I found another example:

  define dso_local <4 x i64> @foo2(<4 x i64> %0, <4 x i64> %1, <4 x i64> %2) {
    %4 = xor <4 x i64> %2, <i64 -1, i64 -1, i64 -1, i64 -1>
    %5 = or <4 x i64> %4, %1
    %6 = or <4 x i64> %0, %1
    %7 = and <4 x i64> %5, %6
    ret <4 x i64> %7
  }

Can we simply it to below in the approach?

  vpor    %ymm1, %ymm0, %ymm0
  vpternlogq      $208, %ymm2, %ymm1, %ymm0
  retq



================
Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:4232
+  if (IsNot(A)) {
+    TernlogMagicA = ~TernlogMagicA;
+    ParentA = A.getNode();
----------------
LuoYuanke wrote:
> pengfei wrote:
> > LuoYuanke wrote:
> > > It seems for VPTERNLOG instruction we can accept the 4th operand whose value is allZero or allOne no matter what is logic operation is.
> > Do you mean the FALSE and TRUE in table 5-10 and 5-11? I think we don't need a VPTERNLOG to generate allZero and allOne.
> VPTERNLOG select all the possible result of 3 bits. I mean it can be extent to 4 bit as long as the 4th bit is compile-time fixed 0 or 1. For this case the node is xor (X, -1), the same approach can be applied to xor(X, 0), and(X, -1), andnp(X, 0) and so on.
But other cases can be simplied directly, e.g. xor(X, 0) -> X, and(X, -1) -> X, andnp(X, 0) -> 0 etc.


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https://reviews.llvm.org/D109295