[PATCH] D109295: [X86] Handle inverted inputs when matching VPTERNLOG from 2 binary ops.

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:4232
+  if (IsNot(A)) {
+    TernlogMagicA = ~TernlogMagicA;
+    ParentA = A.getNode();
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pengfei wrote:
> LuoYuanke wrote:
> > It seems for VPTERNLOG instruction we can accept the 4th operand whose value is allZero or allOne no matter what is logic operation is.
> Do you mean the FALSE and TRUE in table 5-10 and 5-11? I think we don't need a VPTERNLOG to generate allZero and allOne.
VPTERNLOG select all the possible result of 3 bits. I mean it can be extent to 4 bit as long as the 4th bit is compile-time fixed 0 or 1. For this case the node is xor (X, -1), the same approach can be applied to xor(X, 0), and(X, -1), andnp(X, 0) and so on.


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  https://reviews.llvm.org/D109295/new/

https://reviews.llvm.org/D109295