[PATCH] D109295: [X86] Handle inverted inputs when matching VPTERNLOG from 2 binary ops.

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added a comment.

In D109295#2984246 <https://reviews.llvm.org/D109295#2984246>, @RKSimon wrote:

> LGTM but @pengfei might have seen some other cases that D109273 <https://reviews.llvm.org/D109273> would address.

The general approach looks great. I don't have other cases. Thanks Craig.



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Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:4232
+  if (IsNot(A)) {
+    TernlogMagicA = ~TernlogMagicA;
+    ParentA = A.getNode();
----------------
LuoYuanke wrote:
> It seems for VPTERNLOG instruction we can accept the 4th operand whose value is allZero or allOne no matter what is logic operation is.
Do you mean the FALSE and TRUE in table 5-10 and 5-11? I think we don't need a VPTERNLOG to generate allZero and allOne.


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Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:4234
+    ParentA = A.getNode();
+    A = A.getOperand(0);
+  }
----------------
LuoYuanke wrote:
> Is the constant operand canonicalized as operand(1)?
We checked it in line 4225.


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https://reviews.llvm.org/D109295