[PATCH] D109074: [Codegen][TLI][X86] SimplifyMultipleUseDemandedBits(): 0'th vec subreg widening is free, try to perform it earlier

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:822
   case ISD::INSERT_SUBVECTOR: {
     // If we don't demand the inserted subvector, return the base vector.
     SDValue Vec = Op.getOperand(0);
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Move the comment down now that we do other things as well.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:832
+    if (Idx == 0 && Vec.isUndef()) {
+      APInt DemandedSubElts = DemandedElts.trunc(SubVT.getVectorNumElements());
+      if (SDValue NewSub = SimplifyMultipleUseDemandedBits(
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Isn't this the same as DemandedElts.extractBits(NumSubElts, Idx)? Reuse a common variable? 


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  https://reviews.llvm.org/D109074/new/

https://reviews.llvm.org/D109074