[PATCH] D109008: [AMDGPU][NFC] Refactor AMDGPUCallingConv.td
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 31 12:09:55 PDT 2021
rampitec added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:352-353
case CallingConv::AMDGPU_Gfx:
return MF->getSubtarget<GCNSubtarget>().hasGFX90AInsts()
- ? CSR_AMDGPU_HighRegs_With_AGPRs_SaveList
- : CSR_AMDGPU_HighRegs_SaveList;
+ ? CSR_AMDGPU_GFX90AInsts_SaveList
+ : CSR_AMDGPU_SaveList;
----------------
arsenm wrote:
> rampitec wrote:
> > arsenm wrote:
> > > Changing the convention based on the subtarget seems problematic. Do we really need to do this?
> > There is no good way to spill AGPRs on gfx908. On gfx90a you can use it in ld/st.
> Then why not just treat them as scratch registers unconditionally?
To give gfx90a a way to use mfma without too much overhead... But maybe really just do it the same way on both.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109008/new/
https://reviews.llvm.org/D109008
More information about the llvm-commits
mailing list