[PATCH] D109008: [AMDGPU][NFC] Refactor AMDGPUCallingConv.td

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 31 12:05:35 PDT 2021


arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:352-353
   case CallingConv::AMDGPU_Gfx:
     return MF->getSubtarget<GCNSubtarget>().hasGFX90AInsts()
-        ? CSR_AMDGPU_HighRegs_With_AGPRs_SaveList
-        : CSR_AMDGPU_HighRegs_SaveList;
+               ? CSR_AMDGPU_GFX90AInsts_SaveList
+               : CSR_AMDGPU_SaveList;
----------------
rampitec wrote:
> arsenm wrote:
> > Changing the convention based on the subtarget seems problematic. Do we really need to do this?
> There is no good way to spill AGPRs on gfx908. On gfx90a you can use it in ld/st.
Then why not just treat them as scratch registers unconditionally?


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109008/new/

https://reviews.llvm.org/D109008



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