[PATCH] D108732: [AMDGPU] Invert partial vgpr to agpr spill lane order

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D108732#2966072 <https://reviews.llvm.org/D108732#2966072>, @arsenm wrote:

> I don't understand what the problem is. The spilling is all done with 32-bit pieces, so why does the alignment matter?

Say we need to spill v[0:3] like in the added test and we have one agpr available. Current logic will spill v0 into agpr and v[1:3] into scratch.

With mubuf there is no problem, we will issue 3 buffer_store instructions, but with flat scratch it will be a single store of an unaligned register.


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https://reviews.llvm.org/D108732