[PATCH] D108732: [AMDGPU] Invert partial vgpr to agpr spill lane order

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

I don't understand what the problem is. The spilling is all done with 32-bit pieces, so why does the alignment matter?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108732/new/

https://reviews.llvm.org/D108732