[PATCH] D108732: [AMDGPU] Invert partial vgpr to agpr spill lane order

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1189
+    unsigned RemEltSize = EltSize;
+    for (int LaneS = (RegOffset + EltSize) / 4 - 1, Lane = LaneS,
+             LaneE = RegOffset / 4; Lane >= LaneE; --Lane) {
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Should add a comment explaining why this is done in reverse


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108732/new/

https://reviews.llvm.org/D108732